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FTE220 RT334012 1202B E2UMA BR303 10772A 331M25 C18F44
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 100K ECL Logic 4-Bit Programmable Delay Modules
ELECTRICAL SPECIFICATIONS @ 25C
Inherent Delay Time (Step 0) ..................... 2.00 ns + 0.50 ns Delay Per Programming Step ................................ See Table Maximum Programming Delay ................. 2 ns + (15 x Step) Output Rise Time (20% to 80%) ........................ 2.00 ns Max.
IN 22 P4 21
Schematic Diagram
P3 20 P2 19 VEE 18 P1 17
OPERATING SPECIFICATIONS
VEE , Supply Voltage ....................................... -4.2 to -5.7VDC IEE , Supply Current ................................................. 95 mA typ. Logic "1" Input: VIH ......................................... -1.165V min. IIH ........................................... 300 A max. Logic "0" Input: VIL ......................................... -1.475V max. IIL ............................................. 0.5 A min. VOH Logic "1" Voltage Out .................................... -1.025 V min. VOL Logic "0" Voltage Out ..................................... -1.620V max. Storage Temperature Range ............................. -55o to +125oC Operating Temperature Range ................................ 0o to +85oC ** Pin 22, Input is internally connected to 16 standard 100K inputs and is internally terminated by Thevenin equivalent of 100 Ohms to -2V.
Error ref. to 0000 (ns) 0.50 0.50 1.0 1.0 1.0 1.0 1.5 1.5 1.5 3.0 3.0 Initial Delay (ns) 0000 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5
Passive Delay Network Internal Termination 100 Ohm Thevenin to -2V
100K ECL 16 to 1 MUX
Output Buffer
6
7
8
VCC VCCA OUT
TEST CONDITIONS
VEE Supply Voltage ................................................. -4.50 VDC Input Pulse Rise Time ............................................. 2.0ns max. Input Pulse Frequency .................................................. 10 MHz Input Pulse Duty Cycle ...................................................... 50% 1. Measurements made at 25 oC 2. Output Terminated through 50 ohms to -2.00 VDC. 3. Delays measured at 50% level of leading edge.
4-Bit Prog. 100K ECL Part Number
Delay per Step (ns) 0.25 .12 0.50 .25 0.75 .35 1.00 .50 1.25 .60 1.50 .60 2.00 .70 2.50 .70 3.00 .70 4.00 .80 5.00 1.0
Output Delay (ns) Referenced to "0000" per Program Setting (P4*P3*P2*P1) 0000 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0001 0.25 0.50 0.75 1.00 1.25 1.50 2.00 2.50 3.00 4.00 5.00 0010 0.50 1.00 1.50 2.00 2.50 3.00 4.00 5.00 6.00 8.00 0011 0.75 1.50 2.25 3.00 3.75 4.50 6.00 7.50 9.00 0100 1.00 2.00 3.00 4.00 5.00 6.00 8.00 0101 1.25 2.50 3.75 5.00 6.25 7.50 0110 1.50 3.00 4.50 6.00 7.50 9.00 0111 1.75 3.50 5.25 7.00 8.75 1000 2.00 4.00 6.00 8.00 1001 2.25 4.50 6.75 9.00 1010 2.50 5.00 7.50 1011 2.75 5.50 8.25 1100 3.00 6.00 9.00 1101 3.25 6.50 9.75 1110 3.50 7.00 1111 3.75 7.50
PPECL2P25 PPECL2P50 PPECL2P75 PPECL2-1 PPECL2-1.25 PPECL2-1.5 PPECL2-2 PPECL2-2.5 PPECL2-3 PPECL2-4 PPECL2-5
10.50 11.25
10.00 11.00 12.00 13.00 14.00 15.00
10.00 11.25 12.50 13.75 15.00 16.25 17.50 18.75
10.50 12.00 13.50 15.00 16.50 18.00 19.50 21.00 22.50
10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00
10.00 12.50 15.00 17.50 20.00 22.50 25.00 27.50 30.00 32.50 35.00 37.50 12.00 15.00 18.00 21.00 24.00 27.00 30.00 33.00 36.00 39.00 42.00 45.00
12.00 16.00 20.00 24.00 28.00 32.00 36.00 40.00 44.00 48.00 52.00 56.00 60.00
10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00
24-Pin Package with Unused Pins Removed per Schematic. Dimensions inches (mm)
1.300 (33.02) MAX .350 (8.89) MAX .010 (0.25) TYP. .400 (10.16) .020 (0.51) TYP. .100 (2.54) TYP.
PPECL2 9901
.520 (13.21) MAX.
.120 (3.05) MIN. .050 (1.27) TYP.
.030 (0.76) TYP.
Specifications subject to change without notice.
For other values & Custom Designs, contact factory.
Rhombus Industries Inc.
15801 Chemical Lane, Huntington Beach, CA 92649-1595 Phone: (714) 898-0960 * FAX: (714) 896-0971
www.rhombus-ind.com * email: sales@rhombus-ind.com


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